1. Field of the Invention
The present invention relates to a silicon single crystal wafer wherein a size of crystal defect inside the crystal, called grown-in defect, is decreased to the smallest by doping nitrogen and optimizing a cooling rate, a nitrogen concentration and an oxygen concentration when pulling a silicon single crystal by a Czochralski method (hereinafter referred to as "CZ method"), and a method for producing it.
2. Description of the Related Art
As a wafer for fabrication of a device such as a semiconductor integrated circuit, a silicon single crystal wafer grown by a Czochralski method (CZ method) is mainly used. If crystal defects are present in such a silicon single crystal wafer, pattern failure is caused when a semiconductor device is fabricated. Particularly, the pattern width of devices which is highly integrated in recent years is very fine as 0.3 .mu.m or less. Accordingly, even small crystal defects as 0.1 .mu.m may cause defects such as pattern failures in the device, and may remarkably lower a yield and characteristics of the device. Accordingly, a size of the crystal defects in the silicon single crystal wafer have to be decreased as thoroughly as possible.
Recently, it has been reported that the above-mentioned crystal defects called grown-in defect incorporated during growth of the crystal are found in the silicon single crystal grown by CZ method by various measurement methods. For example, these crystal defects in a single crystal grown at a general growth rate in commercial production (for example, about 1 mm/min or more) can be detected as a pit by subjecting the surface of the crystal to preferential etching (Secco etching) with Secco solution (a mixture of K.sub.2 Cr.sub.2 O.sub.7, hydrofluoric acid and water) (See Japanese Patent Application Laid-open (kokai) No.4-192345).
The main cause of generation of such a pit is considered to be a cluster of vacancies which are aggregated during manufacture of single crystal or an oxide precipitate which is an agglomerate of oxygen atoms getting in from a quartz crucible. When these crystal defects are present in the surface portion (at a depth of 0 to 5 .mu.m) in which a device is fabricated, they come to harmful defect to degrade characteristics of the device.
Accordingly, it is desirable to reduce these crystal defects.
For example, it is known that a concentration of the above-mentioned cluster of vacancies can be lowered by decreasing a growth rate of the crystal extremely (for example, to 0.4 mm/min or less) (See Japanese Patent Application Laid-open (kokai) No.2-267195). However, adopting this method, there is generated a crystal defect which is considered to be a dislocation loop formed as a result of new aggregation of excess interstitial silicon atoms, which may degrade characteristics of a device significantly. Accordingly, the problem cannot be solved by the method. Furthermore, productivity of the single crystal and cost performance are extremely decreased in the method, since the growth rate of the crystal is decreased from about 1.0 mm/min as usual or more to 0.4 mm/min or less.